At present, in each of many integrated circuits, a selector circuit is widely used so as to realize a function of selecting one signal from among a plurality of input signals.
FIG. 1 is a diagram illustrating an example of the selector circuit. In FIG. 1, a signal line indicated by a heavy line indicates that the signal line includes a plurality of signal lines. In the other figures, heavy lines are also defined in the same way as in FIG. 1.
A selector circuit 100 illustrated in FIG. 1 includes selection circuits 101 to 104 located at a previous stage, a selection circuit 105 located at a subsequent stage, and a discharge transistor 106, and selects one signal from among 16 input signals IN1 to IN16, and output the signal as an output signal OUT.
Each of the selection circuits 101 to 104 receives four corresponding input signals from among the 16 input signals IN1 to IN16. In addition, each of the selection circuits 101 to 104 receives common selection control signals SEL_L1 to SEL_L4 and a timing control signal P/E. Each of the selection circuits 101 to 104 selects and outputs one signal from among the four received input signals, on the basis of the selection control signal SEL_L1 to SEL_L4.
The selection circuit 105 receives four output signals OUT1 to OUT4 of the selection circuits 101 to 104, and receives selection control signals SEL_H1 to SEL_H4. On the basis of the selection control signals SEL_H1 to SEL_H4, the selection circuit 105 selects one signal from among the four received output signals OUT1 to OUT4, and outputs the selected signal as an output signal OUT.
Here, the circuit operations of the selection circuits 101 to 104 will be described in accordance with a timing chart illustrated in FIG. 2.
In addition, in the present specification and the figures, it is assumed that, form among levels of a digital signal propagating through a circuit, a higher level is indicated by “H” or “1”, and a lower level is indicated by “L” or “0”. An H level and “1” have a same meaning, and an L level and “0” have a same meaning.
In addition, in this chart, for example, a notation “SEL_H1,2,3,4” indicates a set of four signals SEL_H1 to SEL_H4. In addition, a notation “1000” indicates that the SEL_H1 is “1” (H level), the SEL_H2 is “0” (L level), the SEL_H3 is “0” (L level), and the SEL_H4 is “0” (L level). The same notation system is also adopted for the other signals. In addition, the same notation system is also adopted in the other figures.
In the example illustrated in FIG. 2, the selection control signal SEL_H1 is set to “1” (H level), and the remaining SEL_H2 to SEL_H4 are set to “0” (L level). Accordingly, the output signal OUT1 of the selection circuit 101 is selected in the selection circuit 105, and is output as the output signal OUT.
First, at a time t1, the timing control signal P/E is set to an L level, and a precharge period PC starts. In the precharge period PC, in the selection circuit 101, a precharge-use transistor in a charging circuit 107 is turned on. Accordingly, a voltage source VDD and a node N101 are electrically connected to each other, and the node N101 is charged to an H level. The H level of the node N101 is held by the latching function of an output circuit 108. At this time, since the discharge transistor 106 is turned off, the node N101 and ground GND are electrically disconnected from each other.
Next, at a time t2, the timing control signal P/E is set to an H level, and an evaluation period EV starts. In the evaluation period EV, the precharge-use transistor of the charging circuit 107 is turned off. Accordingly, in the selection circuit 101, the node N101 is disconnected from the voltage source VDD. At this time, the discharge transistor 106 is turned on. A discharge control circuit 110 that controls whether or not the node N101 is to be discharged is provided between the node N101 and the transistor 106, and controls whether or not the node N101 and the ground GND are to be electrically connected to each other through the discharge transistor 106.
In the example illustrated in FIG. 2, the selection control signal SEL_L1 is set to “1”, and the remaining SEL_L2 to SEL_L4 are set to “0”. In this case, in the discharge control circuit 110, only a transistor, into the gate of which the selection control signal SEL_L1 is input, is turned on, and transistors, into the gates of which the three remaining selection control signals SEL_L2 to SEL_L4 are input, are turned off. Accordingly, the input signal IN1 corresponding to the selection control signal SEL_L1 is selected.
At this time, since the input signal IN1 indicates “1” (H level), the transistor into the gate of which the input signal IN1 is input is turned on. Accordingly, since the node N101 and the ground GND are electrically connected to each other, the node N101 is discharged to an L level through the discharge control circuit 110 and the discharge-use transistor 106.
The output circuit 108 inverts the L level of the node N101 using an inverter 109, and outputs a signal of an H level, as the output signal OUT1. Namely, in the selection circuit 101, the output signal OUT1 is output that has the same level as the H level (“1”) of the input signal IN1.
The selection circuit 105 selects the output signal OUT1 of the selection circuit 101. Receiving the output signal OUT1 of an H level, the selection circuit 105 outputs the output signal OUT of an H level.
In addition, a technique has been known in which, after charging a signal line to an H level, it is determined, on the basis of the level of an input signal, whether or not the signal line is to be discharged, and thereby outputting a signal of a desired level.
Examples of such a technique are disclosed in Japanese Laid-open Patent Publication No. 06-177751, Japanese Laid-open Patent Publication No. 2001-325050, and Japanese Laid-open Patent Publication No. 10-302479.
However, in the selector circuit illustrated in FIG. 1, in the selection circuits 102 to 104 located at the previous stage, which output the output signals OUT2 to OUT4 that are not selected by the selector circuit 105 located at the subsequent stage, the same circuit operations as that of the selection circuit 101 are also performed. In the same way as the node N101 in the selection circuit 101, in the selection circuits 102 to 104, charge-discharge cycles are also repeatedly executed for nodes N102 to N104, and operations are also repeatedly performed in which output signals having levels corresponding to the levels of the input signals are generated. Therefore, there has been a problem that useless discharge is repeated, an unwanted consumption current occurs, and hence a large amount of electric power is wasted.
In the example illustrated in FIG. 2, even though the output signals OUT2 to OUT4 of the selection circuits 102 to 104 located at the previous stage are not selected by the selection circuit 105 located at the subsequent stage, in the selection circuits 102 to 104, the nodes N102 to N104 are also charged to H levels in the precharge period PC, and the nodes N102 to N104 are discharged to L levels by the H levels (“1”) of the selected input signals IN5, IN9, and IN13 in the evaluation period EV. In addition, a charge operation in the precharge period and a discharge operation in the evaluation period are repeated. As the result of unwanted charge and discharge repeatedly performed for the nodes N102 to N104, an unwanted consumption current occurs.